ICNCE 2026

A large part of the current effort in AI hardware is directed at accelerating linear operations, especially matrix-vector multiplications. Yet the expressive power of artificial neural networks does not arise from linear operations alone. Neural networks are nonlinear function approximators, and their ability to represent complex input-output relations critically depends on nonlinear transformations. This motivates a complementary hardware paradigm in which nonlinear processing itself is implemented directly in physical devices.

Here, I discuss reconfigurable nonlinear-processing units (RNPUs) as silicon-based physical computing primitives for hardware-native nonlinear computation. RNPUs are multi-terminal nanoelectronic devices whose nonlinear input-output characteristics can be tuned by electrical control signals, enabling a single physical substrate to implement many different computational transformations. This approach connects to broader efforts toward adaptive and intelligent matter [1,2] and builds on material-learning concepts [3], but places nonlinear processing at the center.

We have shown that silicon-based RNPUs can perform benchmark classification tasks and that their functionality can be programmed through machine-learning-inspired optimization [4,5]. More recently, we demonstrated gradient descent in materia using homodyne gradient extraction, enabling direct physical optimization of device functionality [6]. We further showed that RNPUs can perform efficient real-time processing of temporal signals, including room-temperature analogue speech recognition [7]. Recent work also demonstrates that RNPUs can serve as physical nonlinear building blocks for Kolmogorov-Arnold Networks, where learnable nonlinear edge functions are implemented in hardware rather than emulated digitally [8].

Together, these results establish RNPUs as a silicon-compatible route toward hardware-native nonlinear computation beyond conventional linear-acceleration paradigms. Recent work by Kareem et al. clarifies the underlying charge-transport mechanism in silicon RNPUs, identifying space-charge effects as the physical origin of their strong and tunable nonlinear response [9]. These insights provide a route toward planar silicon implementations with engineered doping profiles, reducing reliance on etched structures and interface traps while strengthening compatibility with CMOS fabrication.

References
[1] C. Kaspar et al., Nature 594, 345 (2021).
[2] H. Jaeger et al., Nat. Commun. 14, 4911 (2023).
[3] S.K. Bose, C.P. Lawrence et al., Nat. Nanotechnol. 10, 1048 (2015).
[4] T. Chen et al., Nature 577, 341 (2020).
[5] H.-C. Ruiz Euler et al., Nat. Nanotechnol. 15, 992 (2020).
[6] M.N. Boon, L. Cassola et al., Nat. Commun. 16, 10272 (2025).
[7] M. Zolfagharinejad et al., Nature 645, 886 (2025).
[8] M. Escudero et al., arXiv:2602.07518 (2026).
[9] J. Kareem et al., arXiv:2605.13477 (2026).