ICNCE 2026

Information technology is undergoing a profound transformation: traditional, command-based data processing and CMOS technology, in which algorithms act like recipes to produce deterministic results, are increasingly being complemented and, in some areas, replaced by AI-based approaches. These approaches rely on machine learning and the automated extraction of knowledge from data, yielding results that are inherently probabilistic. Data processing in such systems is based on artificial neural networks (ANNs), inspired by neuroscience, whose operation relies on threshold-like computational elements and artificial synapses. A key challenge of this development is the rapidly growing energy demand of modern computing systems.
In our projects, we investigate memristive devices and systems for neuromorphic computing (NC) that have the potential to operate far more energy-efficiently than conventional computer architectures. The focus is placed on the development and analysis of redox-based memristive elements.
The lecture outlines the physical principles underlying these devices and illustrates how materials science and electrical engineering draw inspiration from the remarkable energy efficiency of the human brain—a topic intensively studied in neuroscience. Insights gained from this research are incorporated into the development of future computer hardware, which can subsequently be exploited in computer science and AI applications. We will demonstrate how such an interdisciplinary approach—bridging neuroscience, materials science, electrical engineering, and computer science—can make a decisive contribution to the realization of energy-efficient neuromorphic systems.
In addition, selected applications of AI will be presented, and their opportunities and risks at both the individual and societal levels will be briefly discussed. Finally, we will reflect on the question of whether future AI systems could develop some form of consciousness, thereby bringing the discussion back to the field of brain research.

Speaker:
Rainer Waser received his PhD in Physical Chemistry from the Technical University of Darmstadt in 1984. He subsequently joined the Philips Research Laboratories in Aachen before being appointed Professor at the Faculty of Electrical Engineering and Information Technology at RWTH Aachen University in 1992. In 1997, in parallel with his university appointment, he assumed the position of Director of the Institute for Electronic Materials at Forschungszentrum Jülich. His scientific work focuses on the physicochemical fundamentals of functional oxide materials — initially on their dielectric and ferroelectric properties, and later in particular on redox-based resistive switching phenomena. His research made substantial contributions to the development of memristive devices, which are now regarded as key candidates for non-volatile memory technologies, computing-in-memory architectures, and neuromorphic hardware systems. Together with Professor Matthias Wuttig and Regina Dittmann, he coordinated the Collaborative Research Center SFB 917 on “Resistively Switching Chalcogenides for Future Electronics,” funded by the German Research Foundation (DFG) from 2011 to 2023 and involving 14 institutes. In 2014, he received the Gottfried Wilhelm Leibniz Prize awarded by the DFG for his interdisciplinary contributions to the physics and materials science of emerging memory technologies. In 2019, he initiated the BMBF-funded structural transformation project “Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future in the Rhineland Region (NEUROTEC)” and – together with Max Lemme – he organized the ICNCE 2024.

This tutorial is an introduction to neuroanatomy and neurophysiology for engineers and computer scientists. We will work our way down from the whole brain to individual neurons and synapses, focusing on where things are and how they work. No prior training in biology is required.

Speaker:

Abigail Morrison is the group leader of “Computation in Neural Circuits” at IAS-6, Jülich Research Centre and a professor at the Faculty of Computer Science at RWTH Aachen. She holds a master’s degree in artificial intelligence and received her PhD in computational neuroscience in 2006 from the University of Freiburg, Germany. Between 2006 and 2009 she was a scientific researcher at the RIKEN Brain Science Institute in Wako-Shi, Japan; she subsequently held a junior professorship at the University of Freiburg, Germany, as well as a group leadership at the Bernstein Center Freiburg, Germany from 2009 to 2012. In 2012 she moved to the Jülich Research Centre, where, in addition to leading her computational neuroscience group in IAS-6, she was the scientific lead of the Simulation and Data Laboratory Neuroscience at the Jülich Supercomputing Centre until 2023. She was appointed to a professorship at the Ruhr University of Bochum in 2012 until moving to RWTH Aachen in 2020. Her neuroscientific research interests include learning, representation and self-organization in spiking neural networks, with a secondary technical focus on neuromorphic computing and the software ecosystem for high-performance neural network simulation.

Various applications demand more and more powerful machine inference in resource-scarce distributed devices. To allow intelligent applications at ultra-low energy and low latency, one needs 1.) custom AI processors, exploiting parallelism and data reuse under strong resource limitations; 2.) efficient ML models, optimized for the target hardware platform; 3.) data-efficient scheduling techniques and algorithm-to-hardware mapping tools. This talk will zoom into such a future of cross-layer optimized AI platforms for edge computing.

Deep neural networks (DNNs) outperform cortical network models in behavioural performance. DNNs also outperform cortical neuron models in terms of their statistical response properties. Yet, the alignment of DNNs with cortical circuits, cortical structures, and synaptic plasticity is rather limited. I present a functional bottom-up model of cortical pyramidal neurons and cortical circuits that is inspired by self- and cross-attention networks in artificial intelligence (AI). I show how cortical layer 2/3 pyramidal neurons can sustain a key-value memory that is queried by cortical layer 5 neurons. The AI-inspired self-attention is implemented as a gain modulation in cortical pyramidal neurons. Crucially, synapses in the cortical key-value memory are frozen, so that the network is learned purely online, without need of backpropagation through time (BPTT). I show how this online plasticity, in principle,could be implemented via dedicated cortical error neurons. I also show how reward-prediction errors (RPEs), calculated in basal ganglia, help in task-switching. Via gain modulation, the RPEs increase the signal-to-noise ratio in the cortical networks. RPEs further gate the recruitment of hippocampal memories and their inclusion in the cortical key-value memories. Overall, the model aligns well with cortical structures involved in cognition, and offers a mechanistic explanation of inference and learning.

Biological intelligence is remarkably data- and energy-efficient. We strive to understand and replicate this in artificial intelligence. A key step toward this goal is to develop robust, scalable learning algorithms for physical and biologically inspired neural networks.Achieving this requires rethinking fundamental principles of representation learning and credit assignment. In this talk, I will present recent work from our group on learning algorithms suited for recurrent, noisy, and resource-constrained substrates. These include, but are not limited to, spiking and neuromorphic systems. I will show how local, biologically plausible learning rules can emerge from self-supervised objectives. I will also discuss applied work on training spiking networks for ultra-low-power brain-machine interfaces.

Many real-life problems — from combinatorial optimization and constraint satisfaction to inference in energy-based AI models — share a common mathematical structure: finding configurations that minimize a complex, non-convex energy landscape. Boolean satisfiability SAT (or MaxSAT), canonical NP-complete (or NP-hard) problems, exemplify this class: the task is to find assignments of Boolean variables satisfying the maximum number of logical constraints. Despite their ubiquity, no efficient algorithm is known for these problems in the worst case. We show that this broad class of problems admits a unified treatment through continuous-time dynamical systems (CTDS) in the form of ordinary differential equations. Our analog solver operates as an energy-based reasoning machine; however, instead of performing static gradient descent, it generates a deterministic, history-weighted gradient flow on a dynamically evolving energy landscape. Unsatisfied constraints accumulate exponentially growing tension via auxiliary variables, continuously reshaping the effective landscape and enabling escape from spurious local minima — a mechanism fundamentally distinct from both standard gradient descent and stochastic Langevin dynamics. Hardness in this framework appears as transient chaos governed by a chaotic repeller. We will briefly discuss the mathematical foundations of analog, continuous-variable computation in continuous time — its advantages, and limitations. We then present CTDS variants, some inspired by experimentally observed many-body neuronal interactions and discuss implications for energy-based AI reasoning, where the same history-weighted dynamics may offer a principled alternative to stochastic sampling for inference in learned energy landscapes.

A large part of the current effort in AI hardware is directed at accelerating linear operations, especially matrix-vector multiplications. Yet the expressive power of artificial neural networks does not arise from linear operations alone. Neural networks are nonlinear function approximators, and their ability to represent complex input-output relations critically depends on nonlinear transformations. This motivates a complementary hardware paradigm in which nonlinear processing itself is implemented directly in physical devices.

Here, I discuss reconfigurable nonlinear-processing units (RNPUs) as silicon-based physical computing primitives for hardware-native nonlinear computation. RNPUs are multi-terminal nanoelectronic devices whose nonlinear input-output characteristics can be tuned by electrical control signals, enabling a single physical substrate to implement many different computational transformations. This approach connects to broader efforts toward adaptive and intelligent matter [1,2] and builds on material-learning concepts [3], but places nonlinear processing at the center.

We have shown that silicon-based RNPUs can perform benchmark classification tasks and that their functionality can be programmed through machine-learning-inspired optimization [4,5]. More recently, we demonstrated gradient descent in materia using homodyne gradient extraction, enabling direct physical optimization of device functionality [6]. We further showed that RNPUs can perform efficient real-time processing of temporal signals, including room-temperature analogue speech recognition [7]. Recent work also demonstrates that RNPUs can serve as physical nonlinear building blocks for Kolmogorov-Arnold Networks, where learnable nonlinear edge functions are implemented in hardware rather than emulated digitally [8].

Together, these results establish RNPUs as a silicon-compatible route toward hardware-native nonlinear computation beyond conventional linear-acceleration paradigms. Recent work by Kareem et al. clarifies the underlying charge-transport mechanism in silicon RNPUs, identifying space-charge effects as the physical origin of their strong and tunable nonlinear response [9]. These insights provide a route toward planar silicon implementations with engineered doping profiles, reducing reliance on etched structures and interface traps while strengthening compatibility with CMOS fabrication.

References
[1] C. Kaspar et al., Nature 594, 345 (2021).
[2] H. Jaeger et al., Nat. Commun. 14, 4911 (2023).
[3] S.K. Bose, C.P. Lawrence et al., Nat. Nanotechnol. 10, 1048 (2015).
[4] T. Chen et al., Nature 577, 341 (2020).
[5] H.-C. Ruiz Euler et al., Nat. Nanotechnol. 15, 992 (2020).
[6] M.N. Boon, L. Cassola et al., Nat. Commun. 16, 10272 (2025).
[7] M. Zolfagharinejad et al., Nature 645, 886 (2025).
[8] M. Escudero et al., arXiv:2602.07518 (2026).
[9] J. Kareem et al., arXiv:2605.13477 (2026).

Biological synapses do more than change their strength: they also regulate how changeable they should remain. This “plasticity of plasticity,” or metaplasticity, is thought to help neural systems balance memory retention with flexibility. While the underlying biological mechanisms remain only partly understood, this idea offers a powerful inspiration for neuromorphic AI: a useful learning system should not only update its synapses, but also decide which synapses should stay plastic, which should consolidate, which information should fade, and when new evidence is worth acquiring.

This talk develops that idea through a Bayesian view of metaplasticity. The central proposal is that uncertainty can act as a local synaptic control signal. Rather than treating uncertainty as an external diagnostic computed after training, we embed it into the learning rule itself. Uncertain synapses remain adaptable, confident synapses are protected from unnecessary change, and outdated information can relax through controlled forgetting. This creates a bridge between bio-inspired principles, continual learning, and neuromorphic hardware constraints, where memory is finite, synaptic writes are costly, and stochasticity is unavoidable.

I will first introduce MESU, Metaplasticity from Synaptic Uncertainty [1]. Inspired by the idea that synapses may carry not only a weight but also an “error bar” on that weight, MESU derives a continual-learning rule in which each parameter update is scaled by synaptic uncertainty. A bounded-memory Bayesian formulation adds controlled forgetting, allowing networks to avoid both catastrophic forgetting and excessive rigidity, without relying on explicit task boundaries. MESU therefore turns synaptic uncertainty into a mechanism for balancing plasticity, consolidation, and adaptation.

I will then present BiMU, Binary Metaplasticity from Uncertainty [2]. BiMU brings the same principle to binary Bayesian neural networks, where the connection to neuromorphic systems is especially direct: synapses have minimal precision, updates are expensive, and stochastic sampling is cheap. By preventing binary posterior saturation, BiMU keeps synapses from becoming permanently frozen and preserves useful epistemic uncertainty. This uncertainty can then drive active continual learning: the system requests labels and performs updates only when stochastic network samples disagree.

Together, MESU and BiMU suggest a neuromorphic view of learning in which finite precision, stochasticity, and forgetting are not necessarily limitations, but computational resources.

[1] D. Bonnet, K. Cottart, T. Hirtzlin, T. Januel, T. Dalgaty, E. Vianello, D. Querlioz, "Bayesian continual learning and forgetting in neural networks", Nature Communications, 16(1), 9614 (2025).

[2] K. Cottart, T. Ballet, D. Bonnet, D. Querlioz, “Active Continual Learning with Metaplastic Binary Bayesian Neural Networks”, ICML, 2026.

This talk explores our success and failures with neuromorphic language models and their deployment on Intel Loihi 2. We have achieved the first billion parameter LLMs running on neuromorphic hardware at 2-watts, moving state-of-the-art reasoning from the datacenter to the edge. We have spent a painful amount of time working out when neuromorphic LLMs do and don't make sense, and our findings have flipped some of our assumptions about how sparsity should be used in these models.

Modern AI spans an increasingly diverse set of model architectures and computational workflows. Different types of models, such as large language models, multimodal systems, diffusion models, and world models, exhibit distinct computational characteristics. Different workflows such as training, reinforcement learning, and inference also have different demands for compute infrastructure. Despite this diversity, today's AI infrastructure, from hardware to core frameworks and libraries, remains largely homogeneous. To maintain computational efficiency, we impose uniformity of primitives - we force diverse mathematical structures of different models into rigid, dense matrix multiplications (GEMM).

This talk presents a first-principles analysis of the relationship between modern AI workloads and hardware topologies. We examine how different model architectures and computational workflows result in distinct computational patterns, and how those patterns translate into requirements for compute, memory, and communication. We compare alternative hardware approaches, from HBM-centric accelerators to ultra-high-bandwidth SRAM-based architectures, and explore the trade-offs they make across diverse workloads.

The central argument is that no single hardware architecture can efficiently serve the full spectrum of modern AI. As workloads diversify, forcing them onto uniform compute platforms leads to increasing inefficiency, cost, and wasted resources. The next era of AI progress will depend on tighter co-design between algorithms and hardware, enabling increasingly heterogeneous computing systems that align computational structure with the hardware best suited to execute it. Ironically, AI itself may accelerate this transition by reducing the cost of developing specialized hardware and software, making heterogeneity not only technically desirable, but economically practical.

Oxide-based memristors are emerging as key enabling technologies for neuromorphic hardware and unconventional computing paradigms. These devices can emulate biological synaptic and neuronal functionalities, while also serving as compact computational units for in-memory processing and
reservoir computing architectures [1].
In this talk, I will present an overview of our recent work on two-terminal oxide memristors and three-terminal ionic transistors, also known as electrochemical random-access memories (ECRAMs). The discussion will focus on materials and device engineering, switching mechanisms, and strategies to
exploit their intrinsic properties for brain-inspired computing primitives and unconventional information processing.
In the first part, I will demonstrate how the programmable and nonlinear characteristics of non-volatile resistance switching Pt/HfO₂/TiN memristors can be leveraged to implement a memristor-driven circuit enabling single-node reservoir computing [2]. This approach efficiently addresses nonlinear classification tasks and real-time information processing. The second part of the presentation will focus on volatile electrochemical memristors based on Ag/SiOₓ/Pt structures [3,4], and how their properties can be tailored by inserting an ultrathin Al₂O₃ layer (1–2 nm), deposited by atomic layer
deposition at the SiOₓ/Ag interface (Figures 1a,b). I will discuss how the interplay between switching kinetics and relaxation dynamics governs device operation, and how engineering multiple relaxation time scales which are crucial for brain-inspired temporal information processing.
Finally, I will introduce our ongoing work on three-terminal ECRAM devices based on WO₃/HfO₂/WO₃ stacks. These devices exhibit bulk, gate-controlled ionic switching, enabling analog, linear, and energy-efficient conductance modulation, which is highly promising for future
scalable neuromorphic systems.

[1] A. Mehonic et al., APL Materials 12, 109201, 2024
[2] M. Escudero et al., Adv. Intell. Syst. 8, 2500508, 2026
[3] M. Dutta et al., Adv. Electron. Mater. 10, 2400221, 2024

abstract: Neuromorphic devices are transforming healthcare by enabling innovative, low-
power, and efficient solutions for biomedical applications. Inspired by the neural architecture and
computational principles of the human brain, these systems are particularly suited for wearable and
implantable technologies capable of real-time, closed-loop interaction with biological tissue while
operating directly at the edge. In this talk, I will introduce the key features of neuromorphic circuits for
healthcare applications, highlighting how they enable energy-efficient edge computing for continuous
sensing, adaptive processing, and autonomous decision-making. I will present examples of neural
computational primitives for biomedical signal processing and discuss their integration into closed-
loop systems combining artificial and biological intelligence.
By leveraging neuromorphic sensing, spiking neural networks, and edge AI, we can develop next-
generation healthcare technologies, from wearable monitoring platforms to implantable
neuroprosthetic devices, that improve patient care, support personalized medicine, and revolutionize
chronic disease management.

The explosive growth of transformer-based AI models and the push toward adaptive intelligence at the edge have exposed fundamental limits of conventional von Neumann hardware, where data movement—not computation—dominates energy and latency. This talk presents recent progress from our group on memory-centric co-design spanning devices, circuits, and architectures to address these challenges for two key AI primitives.
First, we reformulate attention score computation as massively parallel in-memory similarity search using Flash-based Content-Addressable Memory (FlashCAM). High-uniformity amorphous oxide semiconductor Flash devices (>95% yield, 4 V memory window) with optimized speed–retention–endurance characteristics have been realized and integrated into 16×16 CAM arrays. A custom PCB measurement platform with Arduino/Jetson control has been developed to demonstrate matchline discharge dynamics that directly encode similarity scores.
Second, we introduce a family of CMOS-compatible non-filamentary memristors (graphene- to metal-insulator-metal stacks) engineered for BEOL monolithic 3D integration and edge continual learning. Latest devices achieve 100 ns switching at 2.5 V while maintaining >100 s retention, high uniformity via via-hole structures, and low cycle-to-cycle variation that enables verification-free programming. We experimentally validate a deterministic outer-product parallel programming scheme on 6×6 subarrays within 32×32 crossbars, achieving O(1) weight updates. Supported by generalizable compact models and macro architectures that emulate floating-point operations for BF16-quantized LoRA adapters, these primitives enable accurate in-situ LLM fine-tuning with minimal accuracy loss.
Together, these results demonstrate practical hardware pathways that dramatically reduce data movement for attention mechanisms and enable efficient on-device adaptation, offering a cohesive device-to-architecture framework for next-generation AI accelerators.